The Art of CMOS Stitching: Challenges and Solutions
CMOS stitching is a specialized technique in semiconductor manufacturing that allows the creation of large sensors and chips by "stitching" together smaller sections of a chip design. This method is essential in fields like medical imaging and industrial cameras, where larger CMOS sensors are needed.
However, much like sewing, achieving a flawless integration of these sections requires extreme precision. In the following text, a Project Manager and an Integrated Circuit Layout Design Engineer from ISDI Sensors R&D Austria delve into the various challenges associated with CMOS stitching. They highlight why this technique remains essential despite its inherent complexity.
The stitching blocks drawn on lithographic masks used for the production of the image sensor
The Challenges of Stitching: From Fabrics to CMOS
When we hear the word “stitching,” many of us think of threads and fabrics, of pulling two pieces together to make something bigger and stronger. But in the world of semiconductor technology, stitching has a whole new meaning, and instead of creating a fine garment, we’re crafting something even more complex: a larger CMOS (Complementary Metal-Oxide-Semiconductor) sensor or ASIC (Application-Specific Integrated Circuit).
Much like sewing fabric, CMOS stitching brings together smaller sections of a chip design into a seamless whole. This process enables the creation of larger chips that would otherwise be impossible to manufacture due to the physical limitations of photolithography tools. But, as with any good tailor, achieving the perfect stitch is easier said than done.
An 8-inch wafer containing a single stitched image sensor
What is CMOS Stitching For?
Stitching is a process used in semiconductor manufacturing to create large-scale sensors or chips by "stitching" together smaller regions, or reticles, of a chip design. The goal is to extend the dimensions of a single CMOS sensor beyond the size limits of the photolithographic equipment. Without stitching, creating larger sensors such as those used in industrial cameras, medical imaging devices, or large-format scanners would be impractical, if not impossible.
For example, in a large-format CMOS sensor, the photomask (which defines the chip pattern) is only as large as the exposure field of the lithography equipment, which is typically limited to around 26 x 33 mm. CMOS stitching allows designers to bypass this constraint, enabling the production of sensors and ASICs that can measure multiple times larger than a single reticle size.
A wafer containing a single stitched image sensor
How is CMOS stitching achieved?
In the stitching process, the design is split into smaller sections called “sub-reticles,” each fitting within the lithographic tool’s field. These sub-reticles are precisely aligned and exposed on a silicon wafer in sequence, carefully "stitching" them together so that the transitions between sub-reticles are seamless.
Why is it so difficult?
Like trying to make an intricate quilt, stitching CMOS designs comes with several challenges.
“The biggest challenge is ensuring that each sub-reticle aligns perfectly with its neighbours.”
A misalignment of even a few nanometres can create defects that render the entire chip unusable. Seamless stitching is critical for maintaining electrical continuity and avoiding functional issues.
Designing circuits that will be stitched requires a different approach. Engineers must ensure that the circuitry along the edges of each sub-reticle can be smoothly integrated with its counterpart in the neighbouring sub-reticle. This often requires special layout techniques and additional verification steps.
Ensuring precise alignment for seamless integration
The key to successful stitching is in the alignment and the overlap zones between these sections. If the stitching is not perfectly aligned, defects can occur where one sub-reticle meets another. Advanced lithography tools and software are used to control the alignment, but even the smallest error can lead to defects at the seam.
Challenges in signal routing and circuit design
Of course, there is a lot to take care about in the product design and the mask layout phases.
The designers have to play tricks with the signal routing to be able to address the repeating identical blocks in both X and Y directions.
The distances are huge between circuit elements, so parameter matching is not something to count on. The parasitics tend to be very large on the long lines and have always to be taken into consideration, even for relatively small current levels and low frequencies. A lot of modelling is involved since the parasitic extracted netlist would often be difficult to handle.
Modularity in design for large silicon areas
The design has to be modular, since such a large silicon area would be impossible to verify if the tools would need to “flatten” the cells instead of checking them hierarchically. We are talking of thousands of ADCs and millions of pixels, just to mention two of the core components of the device.
Managing the stitching region in layout design
In layout design, defining a stitching region on the edges of sub-reticles is crucial to ensure seamless transitions and avoid open connections or short circuits between them.
This region helps prevent open connections and shorted lines, but it also introduces additional complexity. A "Stitch-layer" of specified size must be drawn, and different design rules apply within this region, demanding careful attention to certain distances.
The stitching plan showing the arrangement of the blocks that compose the image sensor
Handling signal crossings and avoiding design rule violations
One stringent rule is the prohibition of vias within this region. Additionally, signals crossing the stitching region must always overlap to ensure continuity, whereas signals not intended to pass through must maintain a specified distance from this area. These and other intricate rules are documented in the Design Manual.
At the top level - where all sub-reticles are assembled - there can still be instances of open connections or shorts.
The importance of design rule checks and layout consistency
These issues are identified through Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks. To minimize such violations, careful planning and routing of crossing signals, along with consistent alignment checks between reticles, are imperative throughout the layout process.
Ensuring consistency with repeated patterns check
The final critical step is the Repeated Patterns Check, where identical reticles are examined for consistency in vertical and horizontal rows to identify any mismatches. Any discrepancies found must be corrected to maintain uniformity. Creating a layout for the stitching process is indeed challenging, requiring diligent adherence to numerous restrictions.
The low yield problem, when bigger isn't always better
One of the major consequences of stitching is the risk of lower yields. As the size of the stitched chip increases, so does the likelihood of defects. Large ASICs and sensors are particularly vulnerable to yield issues because a single defect in one sub-reticle can ruin the entire device.
Imagine trying to sew a massive quilt out of dozens of tiny squares. If just one square is off, the entire quilt looks distorted - or worse, it falls apart. In semiconductor manufacturing, this translates to expensive losses, as companies may only get a handful of functional devices from a wafer that could have produced hundreds of smaller chips. Now, imagine us, having a single device per wafer. Scary!
“ Ask any CMOS engineer – they will tell you, that stitching is a ‘seamless’ process… until it´s not.”
Stitching... one way or another
In the world of CMOS stitching, engineers are part technologist, part artisan, trying to bring together sub-reticles as seamlessly as a tailor stitching fabric. But like an overly ambitious seamstress trying to make a dress from mismatched patterns, things don’t always go as planned. The challenges of alignment, complexity, and low yield can make the process feel less like high-tech engineering and more like threading a needle in the dark.
And if you're wondering if stitching is difficult, just ask any CMOS engineer - they’ll tell you it's a "seamless" process... until it's not. It takes years to perfect your stitching skills, one way or another!